The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, and in particular, relates to measures for improving the reliability of the semiconductor device.
In recent years, with the scaledown and operation speedup of LSIs, reduction in the sizes of individual parts of a MISFET of an LSI according to scaling rules have been requested. In particular, it has become increasingly necessary to reduce the margin between the gate electrode and the contacts to the active regions as the source/drain of the MISFET. In general, in a self-alignment contact (SAC) structure in which source/drain contacts are allowed to overlap a gate electrode and sidewalls, it is necessary to prevent short-circuiting between the contacts and the gate electrode and short-circuiting between the contacts and regions of the semiconductor substrate right under the sidewalls. For this purpose, a gate-top protection film and the sidewalls of the gate electrode are made of a silicon nitride film because the silicon nitride film has a high dry-etching selective ratio with respect to an oxide film constituting an interlayer insulating film.
FIGS. 8A to 8C are cross-sectional views showing a conventional fabrication process of a p-channel MISFET of the SAC structure having a poly-metal gate electrode. In general, an n-channel MISFET is also formed in another region although illustration of the fabrication process thereof is omitted in FIGS. 8A to 8C.
Referring to FIG. 8A, a silicon oxide-nitride film serving as a gate insulating film is formed on the principal plane of a Si substrate 101. A polysilicon film is then deposited on the silicon oxide-nitride film by LPCVD. During this deposition, the polysilicon film is also deposited on the back surface of the Si substrate as a back polysilicon film 120. Boron ions (B+) as p-type impurity ions are implanted in a portion of the polysilicon film on the principal plane side located in a p-channel MISFET formation region under the conditions of an accelerating energy of 5 keV and a dose of 3xc3x971015 cmxe2x88x922. Note that in general n-type impurity ions are implanted in an n-channel MISFET formation region. A metal film having a thickness of 50 nm is then deposited by sputtering, and subsequently a silicon nitride film having a thickness of 100 nm is deposited on the metal film. During this deposition, the silicon nitride film is also deposited on the surface of the back polysilicon film 120 on the back side of the Si substrate 101, as a back silicon nitride film 121. Thereafter, the silicon nitride film, the metal film, the polysilicon film and the silicon oxide-nitride film formed on the principal plane side of the Si substrate 101 are patterned by photolithography and dry etching, to form a gate electrode portion 113 essentially composed of a gate insulating film 102, a lower gate electrode 103, an upper gate electrode 104 and a gate-top protection film 105 on the Si substrate 101.
Thereafter, a resist mask is formed covering the n-channel MISFET formation region while leaving the p-channel MISFET formation region open. In this state, boron fluoride ions (BF2+) as p-type impurity ions are implanted in the Si substrate 101 using the gate electrode portion 113 as a mask under the conditions of an accelerating energy of 10 kev and a dose of 3.0xc3x971014 cmxe2x88x922, to form p-type LDD layers 106.
Referring to FIG. 8B, after removal of the resist mask, a silicon nitride film is deposited on the resultant substrate to a thickness of 80 nm by LPCVD. The silicon nitride film is then etched back to form nitride film sidewalls 107 on the sides of the gate electrode portion 113. During this etch-back, a back silicon nitride film 122 formed during the deposition of the silicon nitride film for the sidewalls remains unremoved on the back silicon nitride film 121 on the back side of the Si substrate 101. Thereafter, a resist mask is formed again covering the n-channel MISFET formation region while leaving the p-channel MISFET formation region open. In this state, boron fluoride ions (BF2+) as p-type impurity ions are implanted in the Si substrate 101 using the gate electrode portion 113 and the nitride film sidewalls 107 as a mask under the conditions of an accelerating energy of 50 keV and a dose of 5.0xc3x971015 cmxe2x88x922, to form p-type source/drain regions 108.
The impurities implanted in the LDD regions 106 and the source/drain regions 108 are then activated by rapid thermal annealing (RTA) at 1000xc2x0 C. for 10 seconds.
Subsequently, a Co film having a thickness of 8 nm is deposited on the resultant substrate and subjected to thermal treatment at 500xc2x0 C. for 60 seconds to allow Si to react with Co to form cobalt silicide films 109 on the source/drain regions 108. Unreacted part of the Co film is then removed by etching.
Referring to FIG. 5C, an interlayer insulating film 110 made of a BPSG film having a thickness of 800 nm is deposited on the resultant substrate and smoothed by chemical mechanical polishing (CMP). Contact holes are then formed through the interlayer insulating film 110 to reach the cobalt silicide films 109 on the source/drain regions 108 by dry etching using a resist mask. The contact holes are filled with tungsten and the like to form source/drain contacts 111. During this formation, no margin is set for alignment between the photomask used for the gate electrode patterning and the photomask used for the contact hole formation (self-alignment). Therefore, the size of the MISFET formation region can be reduced.
Thereafter, a metal film such as an aluminum alloy film is deposited on the interlayer insulating film 110 and then patterned to form metal interconnections 112 on the interlayer insulating film 110 to be connected with the source/drain contacts 111.
During the formation of interconnections, heat treatment in a hydrogen atmosphere (hydrogen sintering) is performed at 400xc2x0 C. for 30 minutes, for example, for recovery from a fixed level induced at the interface between the Si substrate 101 and the gate insulating film 102 and a damage layer in the Si substrate 101.
The MIS transistor fabricated in the conventional process described above has the following problems.
In a process step shown in FIG. 8A, the lower gate electrode 103 and the back surface of the Si substrate 101 are subjected to the high-temperature heat treatment in the state that they are covered with the gate-top protection film 105 made of a nitride film and the back silicon nitride film 121. This results in that they receive intense stress from the silicon nitride films. In addition, during the formation of the silicon nitride film by LPCVD, hydrogen enters the silicon nitride film. Such hydrogen fails to be diffused to the outside by being interfered by the silicon nitride film itself and remains inside the gate electrode. With the existence of hydrogen in the gate electrode and also the existence of the stress as described above, intrusion of boron in the gate electrode into the gate insulating film 102 and the Si substrate 101 is facilitated during the activation of the impurities implanted in the source/drain regions 108 and the like. As a result, the flat band voltage of the MIS capacitor may decrease, and this may possibly increases the variation in the threshold voltage of the transistor.
The lower gate electrode 103 and the back surface of the Si substrate 101 are covered with the gate-top protection film 105 made of a nitride film and the back silicon nitride film 121 as described above. This causes another problem of insufficient supply of hydrogen to the gate insulating film 102 and the Si substrate 101 during the hydrogen sintering. As a result, recovery from a fixed level induced at the interface between the Si substrate 101 and the gate insulating film 102 and a damage layer in the Si substrate 101 is insufficient. This may possibly deteriorate the reliability of the semiconductor device, including decrease in hot carrier resistance during actual use of the semiconductor device.
FIG. 9 is a graph showing the gate area dependency of the flat band voltage of a PMIS capacitor. As is found from FIG. 9, the larger the gate area is, the smaller the flat band voltage is. The reason is as follows. The lower gate electrode 103 receives more intense stress from the silicon nitride film as the gate area is larger. Therefore, boron is more easily diffused from the gate electrode into the gate insulating film 102 and the Si substrate 101. As the flat band voltage decreases, the threshold voltage varies among transistors of different sizes. This causes a significantly serious problem for logic circuits.
An object of the present invention is providing a semiconductor device including a MISFET of the SAC structure exhibiting high integrity while maintaining high reliability, and a method for fabricating such a semiconductor device.
The semiconductor device of the present invention includes: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode made of a conductive material formed on the gate insulating film; a gate-top protection film made of an insulating material formed on the gate electrode; source/drain regions formed by implanting impurities in regions of the semiconductor substrate located on both sides of the gate electrode; an interlayer insulating film formed on the resultant substrate; and a gate contact member formed by filling a gate contact hole with a conductive material, the gate contact hole extending through the interlayer insulating film and the gate-top protection film to reach the gate electrode, wherein the gate-top protection film has an opening exposing part of a portion of an area located on the top surface of the gate electrode other than the region of the gate contact hole.
With the above structure, since the gate-top protection film does not cover the entire gate electrode, diffusion of hydrogen in the gate electrode to the outside is facilitated and also stress applied to the gate electrode is relieved. Therefore, intrusion of impurities such as boron in the gate electrode into the gate insulating film and the semiconductor substrate can be suppressed, and thus a highly reliable semiconductor device with a reduced variation in threshold voltage is obtained. In addition, with this structure, hydrogen can be easily supplied to the gate insulating film and the semiconductor substrate via the region of the gate electrode that is not covered with the gate-top protection film during hydrogen sintering in the fabrication process. This facilitates recovery from a fixed level and damage, and thus provides a structure exhibiting high hot carrier resistance during actual use of the semiconductor device.
The gate-top protection film is preferably a silicon nitride film. This provides a structure suitable for enhancing the density of the semiconductor device by adopting the SAC structure.
The semiconductor device may further includes source/drain contact members formed by filling holes with a conductive material, the holes extending through the interlayer insulating film to reach the source/drain regions, wherein the gate-top protection film is left behind only on portions of the area on the top surface of the gate electrode determined considering overlap with the source/drain contact members. Therefore, since the SAC process is possible using the remaining portions of the gate-top protection film, this structure is suitable for attaining a finer device. That is, it is possible to provide a semiconductor device having a structure suitable for size reduction while maintaining high reliability.
Preferably, the opening of the gate-top protection film is part of a dummy contact hole extending through the interlayer insulating film and the gate-top protection film to reach the gate electrode, and the device further comprises a dummy contact member formed by filling the dummy contact hole with a conductive member, the dummy contact member not being used for supply of a voltage to the gate electrode. With the dummy contact member, part of the top surface of the gate electrode is open. Therefore, by performing annealing and hydrogen sintering under the existence of this contact, it is possible to provide a semiconductor device having a structure suitable for facilitated diffusion of hydrogen in the gate electrode to the outside and recovery from a fixed level and damage.
The dummy contact member is preferably larger in cross-sectional area than the gate contact member.
The first method for fabricating a semiconductor device of the present invention includes the steps of: (a) forming a gate insulating film on a semiconductor substrate; (b) depositing a conductive film on the gate insulating film; (c) forming a silicon nitride film covering both surfaces of the semiconductor substrate after the step (b); (d) patterning the conductive film and a portion of the silicon nitride film located on the principal plane side of the semiconductor substrate to form a gate electrode and a gate-top protection film; (e) implanting impurity ions in the semiconductor substrate to form source/drain regions after the step (d); (f) performing annealing for activation of the impurities implanted in the source/drain regions; and (g) removing a portion of the silicon nitride film located on the back side of the semiconductor substrate after the step (c) and before the step (f).
By the above method, in the step of performing annealing for activation of the impurities, application of stress to the gate electrode and the semiconductor substrate is suppressed because the silicon nitride film on the back side of the substrate has been removed. As a result, diffusion of impurities such as boron in the gate electrode can be suppressed, and thus it is possible to fabricate a highly reliable semiconductor device with a reduced variation in threshold voltage.
The method may further include the step of performing hydrogen sintering after the step (f). By the hydrogen sintering, hydrogen can be efficiently supplied to the gate insulating film and the region near the principal plane of the semiconductor substrate via the back surface of the semiconductor substrate. Therefore, it is possible to fabricate a semiconductor device in which recovery from a fixed level and damage is facilitated and high hot carrier resistance is exhibited during actual use of the semiconductor device.
The second method for fabricating a semiconductor device of the present invention includes the steps of: (a) forming a gate insulating film on a semiconductor substrate; (b) depositing a conductive film on the gate insulating film; (c) forming a silicon nitride film covering the principal plane of the semiconductor substrate after the step (b); (d) patterning the silicon nitride film to form a gate-top protection film only on part of an area located immediately above a gate electrode of the conductive film; (e) patterning the conductive film to form the gate electrode; (f) implanting impurity ions in the semiconductor substrate to form source/drain regions after the step (e); (g) performing annealing for activation of the impurities implanted in the source/drain regions; (h) forming an interlayer insulating film on the resultant substrate; and (i) forming contact holes through the interlayer insulating film to reach the source/drain regions, the contact holes overlapping the gate electrode only via the gate-top protection film at any overlap portion with the gate electrode.
By the above method, since the gate-top protection film does not cover the entire gate electrode during the annealing in the step (g), diffusion of hydrogen in the gate electrode to the outside is facilitated, and also stress applied to the gate electrode during the heat treatment is relieved. Therefore, intrusion of impurities in the gate electrode into the gate insulating film and the semiconductor substrate can be suppressed, and thus reduction in flat band voltage due to the intrusion of impurities is suppressed. It is therefore possible to fabricate a semiconductor device with a reduced variation in threshold voltage.
The method may further include the step of performing hydrogen sintering after the step (g) and before the step (h). During this hydrogen sintering, hydrogen can easily enter the gate insulating film and the semiconductor substrate via the region of the gate electrode that is not covered with the gate-top protection film. This facilitates recovery from a fixed level and damage, and thus high hot carrier resistance is exhibited during actual use of the semiconductor device. Moreover, the SAC process is possible using the locally formed gate-top protection film on the gate electrode. Thus, it is possible to fabricate a fine semiconductor device while maintaining high reliability.
The third method for fabricating a semiconductor device of the present invention includes the steps of: (a) forming a gate insulating film on a semiconductor substrate; (b) depositing a conductive film on the gate insulating film; (c) forming a silicon nitride film covering the principal plane of the semiconductor substrate after the step (b); (d) patterning the silicon nitride film and the conductive film to form a gate-top protection film and a gate electrode; (e) implanting impurity ions in the semiconductor substrate to form source/drain regions after the step (d); (f) forming an interlayer insulating film on the resultant substrate after the step (e); (g) forming a contact hole through the interlayer insulating film and the gate-top protection film to reach the gate electrode; and (h) performing heat treatment for activation of the impurities implanted in the source/drain regions after the step (g).
By the above method, since the gate-top protection film does not cover the entire gate electrode during the annealing, diffusion of hydrogen in the gate electrode to the outside is facilitated, and also stress applied to the gate electrode during the heat treatment is relieved. Therefore, intrusion of impurities in the gate electrode into the gate insulating film and the semiconductor substrate can be suppressed, and thus reduction in flat band voltage due to the intrusion of impurities is suppressed. It is therefore possible to fabricate a semiconductor device with a reduced variation in threshold voltage.
The method may further include the step of performing hydrogen sintering after the step (g). During this hydrogen sintering, hydrogen can easily enter the gate insulating film and the semiconductor substrate via the region of the gate electrode that is not covered with the gate-top protection film. This facilitates recovery from a fixed level and damage, and thus high hot carrier resistance is exhibited during actual use of the semiconductor device. Moreover, the SAC process is possible using the locally formed gate-top protection film on the gate electrode. Thus, it is possible to fabricate a fine semiconductor device while maintaining high reliability.
The method may further include the step of forming a barrier metal film over the contact hole and the interlayer insulating film. In this case, the step (h) is preferably performed after the step of forming a barrier metal film. More preferably, the method further includes the step of performing hydrogen sintering after the step of forming a barrier metal film.
The method may further include the step of forming a contact member by filling the contact hole with a conductive material. In this case, the step (h) may be performed after the step of forming a contact member.
In the above case, also, the method preferably further includes the step of performing hydrogen sintering after the step of forming a contact member.
In the step (g), preferably, at least a gate contact hole and a dummy contact hole are formed as the contact hole, the gate contact hole is a hole to be filled with a contact member used for supply of a voltage to the gate electrode, and the dummy contact hole is a hole to be filled with a dummy contact member that is not used for supply of a voltage to the gate electrode.